1. Technical Field
This invention relates in general to communication systems and information and data processing systems, and more particularly, to digital data regeneration and deserialization techniques for such systems.
2. Description of the Prior Art
In optical fiber transmission systems the trend is to increase the data rate further to exploit the high transmission capacity of single-mode optical fibers. The limiting factor for data rate increases is usually not the optical fiber data carrying capability, but rather electronic circuit performance. In digital communication networks, such as fiber optic transmission systems, the data sampling clock signal is usually recovered from the incoming serial data stream. At the communication link receiving end, the transmitted serial data stream must be regenerated and deserialized. In many such communication systems, phase locked loops (PLLs) are used for recovery of the clock signal that corresponds in frequency and phase to the clock of the data stream transmitted through the network and received at the station. Data deserialization is typically accomplished by a special circuit called the deserializer. The PLL and deserializer are considered to be critical components in the data communication network. These circuits traditionally operate at the serial data stream rate and usually limit communication channel data carrying capability.
FIG. 1 depicts a conventional regeneration and deserialization circuit, generally denoted 10. Circuit 10 receives an equalized and amplified serial data signal on data line 12 which is coupled to a PLL circuit 14 and a data latch 16. PLL circuit 14 recovers a clock signal from the serial data stream and data is retimed by latch 16. The clock output 18 of PLL circuit 14 is input to latch 16 and a ring counter 20. Retimed serial data on output line 22 of data latch 16 is then deserialized into Q parallel bits through a plurality of latches 24. This is accomplished by applying regenerated data on line 22 to each data latch 24 via a first input, and the clock signal outputs of different phase from ring counter 20 to respective second inputs of data latches 24. Each serial bit is clocked into a single latch by one of the ring counter's output clocks CLK(1), CLK(2),..., CLK(Q). Once all parallel bits are latched, they are clocked to a second parallel register (not shown) via a clock pulse occurring slightly after the last deserialization clock.
In this conventional regeneration and deserialization circuit embodiment, retiming latch 16 operates at the data clock frequency, "f", while latches 24 function at 1/Qth the data clock frequency, i.e., f/Q. With existing technology, latch 16 is near its limit of operation and relatively unreliable at high data transmission rates. For example, optical fiber transmission systems are capable of operating at a one nanosecond data rate.
The present invention, therefore, is designed to solve this performance limitation of conventional digital data regeneration and deserialization techniques and thus allow for higher data rate signal processing for a given system.